In random access memories, a memory access sequence (for example, a read or write operation) typically proceeds as follows. An activate command opens a row (selected by row address decoding). A read or write command reads/writes data in a column of the open row (or in a corresponding row buffer), and finally a precharge command closes the row and prepares the bank for a next access. Each activate/precharge cycle of a memory component is a stress event, generating electric fields and current flow across junctions, dielectric layers and conductors. Over time, these stress events may lead to a hard failure, particularly in the rows that are accessed most frequently.